Design Engineer
04497

Industry: Electronics

Resides: Arizona

Salary: Open

Relocate: Yes

On the Market:

OBJECTIVE:
To Obtain a challenging position as a RTL/DFT/Physical Design/
Validation/Verification /Application/ Product/Circuit Design Engineer
for high performance microprocessors where I will be able to broaden
my skills.

EDUCATION:

Masters of Science in Electrical Engineering
Major: Solid State Electronics
Arizona State University, Tempe, AZ.
               

Bachelor of Science in Engineering(EEE),
Major: Electrical& Electronics Engineering
Bangladesh University of Engineering and Technology, Dhaka, Bangladesh.
       
WORK EXPERIENCE:

8/00 - present:

AZ

Involved in hardening of several high performance ARM cores (ARM7TDMISrev4, ETM7 Large, ETM7 Medium) in CMOS12.

Projects currently involved with: ARM926EJS (8K instruction and 8K cache, CMOS12, standard vt, 6 metal layer process), ARM926EJS 16k 16K
(16K instruction and 16K data cache, CMOS12, standard vt, 6 metal layer process), Embedded Trace Buffer (CMOS12, standard vt, 3K
integrated RAM), ETM7 Large (CMOS12, high vt, 5 layer metal layer process)

Validated RTL with core specific validation suite using HDL simulation tool (ncsim, modelsim).

Synthesized different ARM cores to achieve optimal performance (using synopsys design compiler).

Validate the prelayout netlist using ARM validation test suite.

Implemented CTAG test wrappers for the ARM cores. (Company) internal checkcore and timnet was used for this purpose

Implemented DFT logic using (Company) cattools (inscan+ timnet).

Performed ATPG using amsal. Expanded the patterns using TPLG, generated testbench using TASS and simulated and verified the
patterns with ncsim, modelsim.

Performed Floorplanning using Silicon Ensemble, Placement and optimization using Ambit-pks, clock tree synthesis using  Ambit-pks,
routing using Silicon Ensemble.

Performed static timing and xtalk analysis using Primetime SI.

Performed parasitic extraction using STARRC-XT and Hyperextract.

Generated sdf and simulated patterns with back annotated timing.

Performed noise analysis using Celtic.

Performed static and dynamic rail analysis using Pwranalysis tool from cadence.

Performed gate vs gate and rtl vs gate validation using Chrysalis,Formality and Verplex.

Performed LVS, DRC, Antenna verification using Calibre, Dracula, Assura.

Generated support files for core delivery like lef, cdl, edtext using Cadence Virtuoso layout editor.

Developed the initial framework for meeting CoReUse compliance level 3 for ARM cores in EPD/ARM- (Arizona).
Actively involved in the development of core hardening flow (both for memory and non memory cores using CMOS18/12 high speed/low leakage library and 5/6 metal layer process technology) for EPD/ARM-Tempe using (Company) QDF 3.2.

Implemented a custom bist engine based on AMDC basic bist algorithm (15N, prelude and bit write enable tests are implemented in RTL) for
ARM926EJS core with 32K data and 32K instruction cache. Performed comparative study on Astro based and sesi + pks based backend design flow.

Developed a flow to generate TLF files from synopsys .lib files using syn2tlf and incorporate the clock tree information from the TLF generated using pearl.

Assisted in training engineers in Arizona and California on EPD/ARM core hardening flow. Developed training documents to serve the purpose.

Actively involved in customer support activity with a broad range of integration issues including implementation of chip level DFT, functional crf testing, and use of simulation models and back-end views.  Conferred with test engineers to execute solutions for
failing test patterns.

Actively participated in project management activities.

02/01-08/01:
Worked as a Design Engineer in Computing & ASIC Business Line of
Company. Responsibilities included development of a top
level wrapper in verilog for EPHY110(CMOS18), selection of I/O pads,
development of IP spec, sdf generation using dcalc from ALF and
extracted parasitics, develop alf files for the design and develop
model for timing annotation, implement CoReUse compliance constraints
to achieve compliance level3 (compliance level 1 was achieved since
CTAG was not implemented for that version of the IP), generating
cshell and perl scripts to automate the sdf generation, simulation.

06/00-12/00:
Worked as a graduate intern in Computing and ASIC BL of (Company). Responsibilities included developing IP spec and test bench to test the functionality for EPHY110.


Academic Projects:

Analog IC Design:
Design of a differential input high frequency feedback amplifier
using HSPICE. Specifications:Vcc=+/-5V, DC gain 40dB+0.1dB, -3dB
bandwidth 100 MHz, unity gain phase margin, fm:greater than 150,large signal
gain flatness: greater than 0.5dB,input offset voltage less than 2mV, slew rate: greater than 1000 volts/ms, output resistance, Rout: greater than 2W, maximum quiescent power
dissipation: less than 100mW, power supply sensitivity : DAvo less than 1dB for Vcc
ranging from +/-4V to +/-6V,source resistance sensitivity:
DAvo/DRs less than 0.1ohm-1


PLL:
Design of a full PLL using simple circuit blocks. This project includes design of PFD, Charge pump, Simple RC filter, VCO and Programmable Divider as a loop feedback element. Simulation was done in HSPICE using TSMC's 0.25-µm process.


Modeling:
Design and simulation of a 32-bit RISC processor. Modeling and simulation was done with VHDL editor and compiler using Mentor Graphic Design Architect.

VLSI Design:
Layout design of a 8 bit risc processor. Mentor graphics tools was used. I was involved in designing the control unit. A 8X8 bit multiplier as part of an application of the processor. We
implemented a FIR multiplier using matirx multiplication as an application of the processor.


Training :  CTAG, Cattools basic, QDF 3.2, Primtime SI, Synthesis with
Synopsys

SOFTWARE PROFICIENCY:

OS:             MS DOS, Windows 95/98/2000, NT, UNIX, LINUX
Languages:      C/C++, FORTRAN, 8085 Assembly language, Visual BASIC, VISUAL
C++, HTML.

Technical:      Synopsys 2002.05-2 (Design Compiler, Test Compiler, VSS),
Primetime SI (2002.03-1), SEDSM, Apollo, Astro, Ambit-PKS,
Ctgen, Ctpks, Ncsim, Modelsim, Celtic, Cattools 3.6,
Dracula, Assura, Calibre, Chrysalis,  Formality, Verplex,
Debussy, HSPICE, VHDL, Verilog.
Scripting       Perl, tcl, cshell.

Strength:       Broad technical background.  Sharp learning curve. Very good
written and verbal communication skills.

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